{"id":38681,"date":"2020-04-23T17:19:42","date_gmt":"2020-04-23T15:19:42","guid":{"rendered":"\/elettronica\/?page_id=38681"},"modified":"2022-04-07T12:54:23","modified_gmt":"2022-04-07T10:54:23","slug":"realizzazioni","status":"publish","type":"page","link":"\/elettronica\/realizzazioni\/","title":{"rendered":"Realizzazioni"},"content":{"rendered":"\n

Alcune Realizzazioni del Centro di Elettronica Bologna<\/strong><\/span><\/p>\n\n\n\n

\u00a0<\/p>\n


\"LUCROD:<\/p>\n

LUCROD: Scheda di readout per esperimenti LHC al Cern<\/span><\/h4>\n
    \n
  • Standard VME 9U con 10 FPGA Intel Cyclone IV<\/li>\n
  • 16 canali analogici con conversione digitale 12 bit fino a 500MS con offset e guadagno programmabili<\/li>\n
  • 16 canali analogici di uscita con offset e guadagno programmabili<\/li>\n
  • 4 Ingressi\/uscite NIM\/TTL<\/li>\n
  • 2 transceiver ottici da 2Gb<\/li>\n
  • Alloggiamento per una scheda TTCrq del Cern<\/li>\n<\/ul>\n
    \n


    \"Polar-FPGA:<\/p>\n

    Polar-FPGA: Scheda di acquisizione dati, progettata per telescopi a raggi cosmici a basso consumo<\/span><\/h4>\n
      \n
    • 1 FPGA Intel Cyclone V<\/li>\n
    • Fino a 32 ingressi LVDS<\/li>\n
    • 2 seriali USB<\/li>\n
    • Interfacciabile con Raspberry Pi, Arduino e moduli GPS<\/li>\n
    • Alloggiamento per una scheda figlia con chip HPTDC del Cern<\/li>\n<\/ul>\n
      \n


      \"Digitizer<\/p>\n

      Digitizer GSPSv2 con Analog Input Board [FAMU]<\/span><\/h4>\n
        \n
      • scheda di conversione analogico-digitale a 8 canali<\/li>\n
      • 4 ADC a due canali AD9684: 14 bit, 500 MS\/s<\/li>\n
      • architettura configurabile tramite mezzanine analogiche che consentono l\u2019interlacciamento<\/li>\n
      • sistema di controllo con Enclustra Mercury+ XU1 con Xilinx’s Zynq UltraScale+\u2122 MPSoC<\/li>\n
      • interfacce: 2 Gigabit Ethernet, USB 3.0, Display Port, SATA<\/li>\n<\/ul>\n
        \n


        \"Scheda<\/p>\n

        Scheda HW switch Box [ATLAS]<\/span><\/h4>\n
          \n
        • Box HV multiplexer con selezione programmabile dei singoli canali di output, per la misura delle curve IV necessarie ai test di qualifica di moduli ibridi del tracciatore ITk.<\/li>\n<\/ul>\n

          160 x 160 x 51.5 mm<\/p>\n

          \n


          \"Scheda<\/p>\n

          Scheda Orbital Detector [FAMU]<\/span><\/h4>\n
            \n
          • Elettronica di front-end per 6 rivelatori basati su LaBr3 accoppiati con fotomoltiplicatori (PMT) Hamamatsu ad alta efficienza quantica<\/li>\n
          • Disposizione dei componenti RADIALE sull\u2019intera scheda<\/li>\n
          • PCB semi-circolare\u00a0 progettato per HV fino a 1500V<\/li>\n
          • Baseline Restorer per ogni singolo PMT<\/li>\n
          • Gestione di tutti i parametri mediante microcontrollers Teensy 3.5 pilotabili da remoto<\/li>\n<\/ul>\n

            366 x 183 mm<\/p>\n

            \n


            \"Breakout<\/p>\n

            Breakout board ad alto rate con connettori Samtec Firefly (Arcadia)<\/span><\/h4>\n
              \n
            • scheda di conversione da connettore FMC a 4 connettori Firefly ECUE<\/li>\n
            • 48 linee differenziali con rate di 640 Mbps<\/li>\n
            • 8 strati<\/li>\n<\/ul>\n

              69 x 60 mm<\/p>\n

              \n


              \"Scheda<\/p>\n

              Scheda rigido-flessibile SiPM Flex per matrici di SiPM [Grant SipMat]<\/span><\/h4>\n
                \n
              • PCB FLEX 4 Layers in Kapton<\/li>\n
              • Tracce a impedenza controllata<\/li>\n
              • Montaggio, del chip BGA (contenente 64 SiPM) e dei connettori, su Kapton<\/li>\n
              • Funzionamento in ambiente criogenico<\/li>\n<\/ul>\n

                458 x 33 x 0.368mm<\/p>\n

                \n

                \"SIPM_AMPLISIPM_AMPLI [SHIP]<\/span><\/h4>\n
                  \n
                • 2 canali\u00a0 Due stadi di amplificazione: 46 dB<\/li>\n
                • 60 mm flex – 90 mm rigid<\/li>\n<\/ul>\n
                  \n


                  \"OPTICAL_RECEIVER_32CH<\/p>\n

                  OPTICAL_RECEIVER_32CH [DARKSIDE]<\/span><\/h4>\n
                    \n
                  • Formato 9U (160×360)<\/li>\n
                  • 32 ingressi ottici analogici<\/li>\n
                  • 32 uscite su connettori MCX<\/li>\n
                  • 64 amplificatori operazionali<\/li>\n<\/ul>\n
                    \n

                    \"Silicon<\/p>\n

                    Silicon Germanium Bipolar RF Transistor [NU@FNAL]<\/span><\/h4>\n
                      \n
                    • Vcc=3V\u00a0 I= 12mA<\/li>\n
                    • Bandwidth \u2248 300MHz<\/li>\n
                    • G= 23dB<\/li>\n
                    • noise : ~160\u00b5V @ 1MHz\u00a0\u00a0(\u2248 6nV\/\u221aHz)<\/li>\n<\/ul>\n
                      \n

                      \"Scheda<\/p>\n

                      Scheda MOTHERBOARD STRIP [DARKSIDE]<\/span><\/h4>\n
                        \n
                      • Kapton PCB – fori ciechi (232×220 mm2)<\/li>\n<\/ul>\n
                        \n

                        \u00a0<\/p>\n

                        \"32<\/p>\n

                        32 Channel Readout board (Nessie)<\/span><\/h4>\n
                          \n
                        • Sensor: SiPM SensL 30035FC 3×3 mm2<\/li>\n
                        • 32 channels<\/li>\n
                        • Input: triaxial cable (~ 1.5 m)<\/li>\n
                        • EASIROC (ampli – shaping\/fast trigger analog serial out<\/li>\n
                        • FPGA: Altera Cyclone III EP3C16Q240C8N (EASIROC and USB handling – data processing for SiPM calibration\/monitoring)<\/li>\n
                        • Out : USB – EASIROC Analog (to Digitizer)<\/li>\n
                        • Main purpose: fast SiPM acquisition – low level signals ( \u2a9d mV)<\/li>\n
                        • Critical design issues:\n
                            \n
                          • custom pitch of input connectors<\/li>\n
                          • signal integrity of PCB traces to EASIROC<\/li>\n
                          • filtering and isolation of all power sections<\/li>\n<\/ul>\n<\/li>\n
                          • 6 Layers – 10 boards (so far)<\/li>\n<\/ul>\n

                            150 x 100 mm<\/p>\n

                            \u00a0<\/p>\n

                            \n

                            \"CATB<\/p>\n

                            CATB (Ship)<\/span><\/h4>\n
                              \n
                            • Sensor:Several SiPM from AdvanSiD (FBK Spin<\/span>-Off) and Hamamatsu<\/li>\n
                            • Test Board mainly for timing studies (goal: resolution < 1 ns)<\/li>\n
                            • 8 channels<\/li>\n
                            • Input: coaxial cable (~2 m)<\/li>\n
                            • Pre-amplification :1 fast out and 1 slow per channel<\/li>\n
                            • 4 layer – 2 boards<\/li>\n
                            • Out : to Digitizer<\/li>\n
                            • Small-size coaxial connectors (MCX)<\/li>\n<\/ul>\n

                              224 x 38 mm<\/p>\n

                              \n

                              \"Photo_Chain<\/p>\n

                              Photo_Chain (A.Montanari)<\/span><\/h4>\n
                                \n
                              • Sensor: SI Photodiode Hamamatsu S1087\/S1133 series<\/li>\n
                              • 4 channels<\/li>\n
                              • INFN Patent<\/li>\n<\/ul>\n

                                150 x 36 mm<\/p>\n

                                \n

                                \"PMT<\/p>\n

                                PMT HV Divider (FAMU)<\/span><\/h4>\n
                                  \n
                                • Sensor: LaBr3 scintillator + PMT<\/li>\n
                                • Active voltage-divider, amplification, power supply<\/li>\n
                                • A unique schematic engineered on 5 distinct PCB due to geometrical detector requirements<\/li>\n
                                • Layout with PADS (Mentor Graphics)<\/li>\n
                                • 2 layers – 20×5 samples<\/li>\n
                                • Critical issues:\n
                                    \n
                                  • cooling (needs carefully component partition to the 5 PCB)<\/li>\n
                                  • connection engineering (multi-board 3D view with PADS)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                                    every board: 45 x 45 mm<\/p>\n

                                    \n

                                    \"Motherboard<\/p>\n

                                    Motherboard (Darkside)<\/span><\/h4>\n
                                      \n
                                    • Sensor: SiPM<\/li>\n
                                    • Board Purpose: collect signals fromfront-end devices<\/li>\n
                                    • Requirement:\n
                                        \n
                                      • good thermal behavior (immersed in Liquid Nitrogen @ ~ -190 \u00b0C)<\/li>\n
                                      • low-radioactivity material<\/li>\n<\/ul>\n<\/li>\n
                                      • First Elec.Division design in Kapton<\/li>\n
                                      • Critical design issues:\n
                                          \n
                                        • SiPM signal integrity (controlled impedance striplines between two ground planes)<\/li>\n
                                        • stackup and material selection<\/li>\n<\/ul>\n<\/li>\n
                                        • 4 Layers – 3 samples (so far)<\/li>\n
                                        • Designed with PADS (Mentor Graphics)<\/li>\n
                                        • Signal integrity simulated with HyperLynx (Mentor Graphics)<\/li>\n<\/ul>\n

                                          215 x 114 mm<\/p>\n

                                          \n

                                          \"DPP<\/p>\n

                                          DPP (FAMU)<\/span><\/h4>\n
                                            \n
                                          • Input: 1 analog-digital conversion channel<\/li>\n
                                          • AD8138: differential input buffer (-3dB BW @ 320 MHz) acting also as anti-aliasing filter<\/li>\n
                                          • ADC: AD9434 12bit @ 500 MS\/s (ENOB: 10.5 up to 250 MHz input – 1.5 Vpp)<\/li>\n
                                          • FPGA Altera Cyclone V 5CGXC5 (digital filtering and data acquisition)<\/li>\n
                                          • Output: Piggy Back Cypress USB 3.0 (max datarate: 5 Gb\/s)<\/li>\n
                                          • 6 layers – 11 board<\/li>\n
                                          • Critical issue: accordion for high-speed USB3 signal from FPGA to Piggy Back connector<\/li>\n<\/ul>\n

                                            65 x 130 mm<\/p>\n

                                            \n

                                            \"Digitizer<\/p>\n

                                            Digitizer Board (Nucl-Ex)<\/span><\/h4>\n
                                              \n
                                            • Input: 2 analog-digital conversion channels<\/li>\n
                                            • Anti-aliasing filter (simulated with SPICE)<\/li>\n
                                            • ADC: AD9255BCPZ-125 14bit @ 125 MS\/s (ENOB: 12 up to 250 MHz input – 2 Vpp)<\/li>\n
                                            • Digital Signal Processor: ADSP-2189NKCAZ-320<\/li>\n
                                            • 6 layers – 50 mezzanine<\/li>\n
                                            • Critical issues:\n
                                                \n
                                              • input from 100 mV to 8 V (managed with multiple voltage controlled amplifiers and analog multiplexers)<\/li>\n
                                              • variable gain and offset (controlled with separated DACs)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                                                140 x 55 mm<\/p>\n

                                                \n

                                                \"GSPS<\/p>\n

                                                GSPS (Elec.Division R&D)<\/span><\/h4>\n
                                                  \n
                                                • FMC mezzanine Card<\/li>\n
                                                • Input: 1 analog-digital conversion channel with 2 interleaved ADC<\/li>\n
                                                • ADA4930 differential buffer coupled in DC with single ended input (6 dB gain)<\/li>\n
                                                • Anti-aliasing filter (simulated with SPICE)<\/li>\n
                                                • ADC: AD9434 12bit @ 500 MS\/s (ENOB: 10.5 up to 250 MHz input – 1.5 Vpp)<\/li>\n
                                                • Output: 12 LVDS x ADC through FMC connector<\/li>\n
                                                • 6 layers – 2 cards<\/li>\n
                                                • Critical issues:\n
                                                    \n
                                                  • filter design<\/li>\n
                                                  • low-jitter clock distribution ( < 1 ps RMS)<\/li>\n
                                                  • reconstruction firmware<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                                                    98 x 70 mm<\/p>\n

                                                    \n

                                                    \"IBL\/PIXEL<\/p>\n

                                                    IBL\/PIXEL ROD (Atlas)<\/span><\/h4>\n
                                                      \n
                                                    • Input : 32 FE-I4 (160 Mb\/s per channel – 5.12 Gb\/s in total )<\/li>\n
                                                    • Control, Data Taking, Monitoring and Calibration<\/li>\n
                                                    • 14-layer 9U x 400 mm VME64x board<\/li>\n
                                                    • 1 Xilinx Spartan6 XC6SLX45-FGG484<\/li>\n
                                                    • 1 Xilinx Virtex5 XC5VFX70T-FF1136: (embedded PowerPC HW core)\n
                                                        \n
                                                      • 2 GByte DDR2 SODIMM<\/li>\n
                                                      • 64 Mbit FLASH Atmel AT45DB642D<\/li>\n<\/ul>\n<\/li>\n
                                                      • 2 Xilinx Spartan6 XC6SLX150-FGG900:\n
                                                          \n
                                                        • 1 2-Gbit DDR2 (Mictor MT47H128M16RT-25E)<\/li>\n
                                                        • 2 1Mx36 SSRAM (Cypress CY7C1370D-250AXC-ND)<\/li>\n<\/ul>\n<\/li>\n
                                                        • Cal: 3 Gbit Ethernet interfaces (PHY: DP83865)<\/li>\n
                                                        • Output: 4 S-Links (5.12 Gb\/s in total)<\/li>\n<\/ul>\n

                                                          360 x 400 mm<\/p>\n

                                                          \n

                                                          \"DRM2<\/p>\n

                                                          DRM2 (ALICE)<\/span><\/h4>\n
                                                            \n
                                                          • Input : TRM board (TDC data from MRPC detector) output through VME<\/li>\n
                                                          • Data Taking, Control, Trigger interface (80 boards foreseen for \u201919 Alice upgrade)<\/li>\n
                                                          • 14 layers – 9U x 160 mm – 5 samples so far (foreseen : ~80)<\/li>\n
                                                          • GBTx from CERN (rad-hard) : serdes @ 4.8 Gb\/s<\/li>\n
                                                          • FPGA: Microsemi Igloo 2 M2GL90T<\/li>\n
                                                          • Output: GBTx (~ 3.2 Gb\/s user payload)<\/li>\n
                                                          • Critical issues:\n
                                                              \n
                                                            • GBTx handling (interface IP core from CERN has been tested yet)<\/li>\n
                                                            • Serdes<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                                                              345 x 162 mm<\/p>\n

                                                              \n

                                                              \"PMT<\/p>\n

                                                              PMT Voltage Divider (Limadou)<\/span><\/h4>\n
                                                                \n
                                                              • Sensor: Hamamatsu R9880U<\/li>\n
                                                              • Limadou calorimeter with Plastic Scintillators<\/li>\n
                                                              • Critical issues:\n
                                                                  \n
                                                                • Small PCBs\/ high voltages : discharges risk<\/li>\n
                                                                • Outgassing<\/li>\n
                                                                • Thermal resistance (made with Kapton-Polyamide)<\/li>\n
                                                                • Redundancy (doubling capacitors)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                                                                  32 x 20 mm<\/p>\n

                                                                  \n

                                                                  \"FMC<\/p>\n

                                                                  FMC mezzanine for DU Base (Km3NET)<\/span><\/h4>\n
                                                                    \n
                                                                  • Near-communication interface board: between the Central Logic Board (CLB) and electronics into (close to) the DU Base<\/li>\n
                                                                  • RS422, RS485, custom protocol on RJ45, FMC to the CLB<\/li>\n
                                                                  • 5 boards so far (foreseen : ~ 100)<\/li>\n
                                                                  • Critical issues:\n
                                                                      \n
                                                                    • galvanic insulation (AC coupling)<\/li>\n
                                                                    • component reliability<\/li>\n
                                                                    • FMC connector mechanics<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                                                                      70 x 50 mm<\/p>\n

                                                                      \n

                                                                      \u00a0<\/p>\n","protected":false},"excerpt":{"rendered":"

                                                                      Alcune Realizzazioni del Centro di Elettronica Bologna \u00a0 LUCROD: Scheda di readout per esperimenti LHC al Cern Standard VME 9U con 10 FPGA Intel Cyclone IV 16 canali analogici con conversione digitale 12 bit fino a 500MS con offset e guadagno programmabili 16 canali analogici di uscita con offset e guadagno programmabili 4 Ingressi\/uscite NIM\/TTL […]<\/p>\n","protected":false},"author":28,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-page-builder-no-sidebar.php","meta":{"_lmt_disableupdate":"no","_lmt_disable":"","footnotes":""},"class_list":["post-38681","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"\/elettronica\/wp-json\/wp\/v2\/pages\/38681","targetHints":{"allow":["GET"]}}],"collection":[{"href":"\/elettronica\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"\/elettronica\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"\/elettronica\/wp-json\/wp\/v2\/users\/28"}],"replies":[{"embeddable":true,"href":"\/elettronica\/wp-json\/wp\/v2\/comments?post=38681"}],"version-history":[{"count":38,"href":"\/elettronica\/wp-json\/wp\/v2\/pages\/38681\/revisions"}],"predecessor-version":[{"id":39611,"href":"\/elettronica\/wp-json\/wp\/v2\/pages\/38681\/revisions\/39611"}],"wp:attachment":[{"href":"\/elettronica\/wp-json\/wp\/v2\/media?parent=38681"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}