{"id":40110,"date":"2024-07-22T14:56:22","date_gmt":"2024-07-22T12:56:22","guid":{"rendered":"\/elettronica\/?page_id=40110"},"modified":"2024-07-22T15:39:37","modified_gmt":"2024-07-22T13:39:37","slug":"highlights-2024","status":"publish","type":"page","link":"\/elettronica\/highlights-2024\/","title":{"rendered":"Highlights 2024"},"content":{"rendered":"\n<h3 style=\"text-align: center\">Highlights 2024<\/h3>\n<p>\u00a0<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40118 size-full\" title=\"FPGA AMD\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-fpga-amd-1.jpg\" alt=\"\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-fpga-amd-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-fpga-amd-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<h4 style=\"text-align: center\"><span style=\"color: #007bb3\">FPGA AMD (EX Xilinx)<\/span><\/h4>\n<ul>\n<li>Spartan 7 (XC7S6 &#8211; 28 nm) ideale per progetti low cost per l\u2019esperimento CMS<\/li>\n<\/ul>\n<p style=\"text-align: center\">\u00a0<\/p>\n<hr \/>\n<p>\u00a0<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40121 size-full\" title=\"Crate per le schede CAEN\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-01-1.jpg\" alt=\"\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-01-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-01-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40125 size-full\" title=\"Crate per le schede CAEN\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-02-1.jpg\" alt=\"\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-02-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-02-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<h4 style=\"text-align: center\"><span style=\"color: #007bb3\">Crate per le schede CAEN<\/span><\/h4>\n<ul>\n<li>Fers A5202 per l&#8217;esperimento Luxe<\/li>\n<li>Riadattamento di cestello commerciale Schroff e backplane progettato ad hoc<\/li>\n<\/ul>\n<hr \/>\n<p>\u00a0<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40128 size-full\" title=\"Prototipo per la validazione ADC\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-prototipo-validazione-adc-1.jpg\" alt=\"\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-prototipo-validazione-adc-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-prototipo-validazione-adc-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<p>\u00a0<\/p>\n<h4 style=\"text-align: center\"><span style=\"color: #007bb3\">Prototipo per la validazione ADC<\/span><\/h4>\n<ul>\n<li>Un canale a 12 bit a 650 Msps<\/li>\n<li>Amplificatori e DAC, per la scheda Lucrod2 per Atlas-Lucid (collegato ad<br \/>una demo board della FPGA Intel Cyclone 10GX &#8211; 10 nm)<\/li>\n<\/ul>\n<hr \/>\n<p>\u00a0<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40133 size-full\" title=\"Scheda per la lettura di due Asic Cern\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-scheda-lettura-asic-cern-1.jpg\" alt=\"Scheda per la lettura di due Asic Cern\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-scheda-lettura-asic-cern-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-scheda-lettura-asic-cern-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<p>\u00a0<\/p>\n<h4 style=\"text-align: center\"><span style=\"color: #007bb3\">Scheda per la lettura di due Asic Cern<\/span><\/h4>\n<ul>\n<li>picoTDC (65 nm, 3 ps resolution) tramite FPGA \u201cnon-volatile\u201d<\/li>\n<li>Microchip PolarFire per Alice3<\/li>\n<\/ul>\n<hr \/>\n<p>\u00a0<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Highlights 2024 \u00a0 FPGA AMD (EX Xilinx) Spartan 7 (XC7S6 &#8211; 28 nm) ideale per progetti low cost per l\u2019esperimento CMS \u00a0 \u00a0 Crate per le schede CAEN Fers A5202 per l&#8217;esperimento Luxe Riadattamento di cestello commerciale Schroff e backplane progettato ad hoc \u00a0 \u00a0 Prototipo per la validazione ADC Un canale a 12 bit [&hellip;]<\/p>\n","protected":false},"author":28,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-page-builder-no-sidebar.php","meta":{"_lmt_disableupdate":"no","_lmt_disable":"","footnotes":""},"class_list":["post-40110","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"\/elettronica\/wp-json\/wp\/v2\/pages\/40110","targetHints":{"allow":["GET"]}}],"collection":[{"href":"\/elettronica\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"\/elettronica\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"\/elettronica\/wp-json\/wp\/v2\/users\/28"}],"replies":[{"embeddable":true,"href":"\/elettronica\/wp-json\/wp\/v2\/comments?post=40110"}],"version-history":[{"count":14,"href":"\/elettronica\/wp-json\/wp\/v2\/pages\/40110\/revisions"}],"predecessor-version":[{"id":40141,"href":"\/elettronica\/wp-json\/wp\/v2\/pages\/40110\/revisions\/40141"}],"wp:attachment":[{"href":"\/elettronica\/wp-json\/wp\/v2\/media?parent=40110"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}