{"id":40136,"date":"2024-07-22T15:26:23","date_gmt":"2024-07-22T13:26:23","guid":{"rendered":"\/elettronica\/?page_id=40136"},"modified":"2024-07-22T15:36:13","modified_gmt":"2024-07-22T13:36:13","slug":"highlights-en-2024","status":"publish","type":"page","link":"\/elettronica\/en\/highlights-en-2024\/","title":{"rendered":"Highlights EN 2024"},"content":{"rendered":"\n<h3 style=\"text-align: center\">Highlights 2024<\/h3>\n<p>\u00a0<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40118 size-full\" title=\"FPGA AMD\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-fpga-amd-1.jpg\" alt=\"\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-fpga-amd-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-fpga-amd-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<h4 style=\"text-align: center\"><span style=\"color: #007bb3\">FPGA AMD (EX Xilinx)<\/span><\/h4>\n<ul>\n<li>Spartan 7 (XC7S6 &#8211; 28 nm) ideal for low cost projects for the CMS experiment<\/li>\n<\/ul>\n<p style=\"text-align: center\">\u00a0<\/p>\n<hr \/>\n<p>\u00a0<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40121 size-full\" title=\"Crate for CAEN borads\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-01-1.jpg\" alt=\"\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-01-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-01-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40125 size-full\" title=\"Crate for CAEN boards\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-02-1.jpg\" alt=\"\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-02-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-crate-schede-caen-02-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<h4 style=\"text-align: center\"><span style=\"color: #007bb3\">Crate for CAEN boards<\/span><\/h4>\n<ul>\n<li>Fers A5202 for the Luxe experiment<\/li>\n<li>Readaptation of Schroff commercial basket and ad hoc designed backplane<\/li>\n<\/ul>\n<hr \/>\n<p>\u00a0<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40128 size-full\" title=\"Prototype for ADC validation\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-prototipo-validazione-adc-1.jpg\" alt=\"\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-prototipo-validazione-adc-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-prototipo-validazione-adc-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<p>\u00a0<\/p>\n<h4 style=\"text-align: center\"><span style=\"color: #007bb3\">Prototype for ADC validation<\/span><\/h4>\n<ul>\n<li>One 12-bit channel at 650 Msps<\/li>\n<li>Amplifiers and DACs, for the Lucrod2 board for Atlas-Lucid (connected to an Intel FPGA demo board Cyclone 10GX &#8211; 10 nm)<\/li>\n<\/ul>\n<hr \/>\n<p>\u00a0<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-40133 size-full\" title=\"Card for reading two Asic Cerns\" src=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-scheda-lettura-asic-cern-1.jpg\" alt=\"Card for reading two Asic Cerns\" width=\"450\" height=\"300\" srcset=\"\/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-scheda-lettura-asic-cern-1.jpg 450w, \/elettronica\/wp-content\/uploads\/sites\/14\/2024\/07\/HL-scheda-lettura-asic-cern-1-300x200.jpg 300w\" sizes=\"auto, (max-width: 450px) 100vw, 450px\" \/><\/p>\n<p>\u00a0<\/p>\n<h4 style=\"text-align: center\"><span style=\"color: #007bb3\">Card for reading two Asic Cerns<\/span><\/h4>\n<ul>\n<li>picoTDC (65 nm, 3 ps resolution) via \u201cnon-volatile\u201d FPGA\u201d<\/li>\n<li>Microchip PolarFire for Alice3<\/li>\n<\/ul>\n<hr \/>\n<p>\u00a0<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Highlights 2024 \u00a0 FPGA AMD (EX Xilinx) Spartan 7 (XC7S6 &#8211; 28 nm) ideal for low cost projects for the CMS experiment \u00a0 \u00a0 Crate for CAEN boards Fers A5202 for the Luxe experiment Readaptation of Schroff commercial basket and ad hoc designed backplane \u00a0 \u00a0 Prototype for ADC validation One 12-bit channel at 650 [&hellip;]<\/p>\n","protected":false},"author":28,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-page-builder-no-sidebar.php","meta":{"_lmt_disableupdate":"no","_lmt_disable":"","footnotes":""},"class_list":["post-40136","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"\/elettronica\/wp-json\/wp\/v2\/pages\/40136","targetHints":{"allow":["GET"]}}],"collection":[{"href":"\/elettronica\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"\/elettronica\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"\/elettronica\/wp-json\/wp\/v2\/users\/28"}],"replies":[{"embeddable":true,"href":"\/elettronica\/wp-json\/wp\/v2\/comments?post=40136"}],"version-history":[{"count":2,"href":"\/elettronica\/wp-json\/wp\/v2\/pages\/40136\/revisions"}],"predecessor-version":[{"id":40139,"href":"\/elettronica\/wp-json\/wp\/v2\/pages\/40136\/revisions\/40139"}],"wp:attachment":[{"href":"\/elettronica\/wp-json\/wp\/v2\/media?parent=40136"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}