Year 2009

July 1: firmware released on July 1 2009

This firmware release is a fixed length 8 bit (5+3) single buffer version without periodical reprogramming of the front end. The attribute field has been modified in such a way that its 3 LSBs are 0s and the fourth one is 1 when AM clock is 40 MHz, 0 when AM clock is 20 MHz.

July 3: firmware of the VP20_VME FPGA released on July 3 2009

This firmware release only changes the VP20_VME code with respect to the previous release. It tries to fix a problem related to the frequent activation of the watchdog protection circuit allowing to reach a ~5 Hz event rate instead of the expected 25 Hz without zero suppression (AM clock = 20 MHz).

July 6: firmware released in July 6 2009

This firmware release fixes a problem of the watchdog circuit when the flow control is asserted by the LDC (for example with the command: eventDump –M :) without zero suppression. The timeout counter is only increased when the LDC flow control is not active.

August 3: firmware released in August 3 2009

This firmware release introduces a better handling of the reset signal and should allow all the boards to be correctly initialized. When running the ttc_init procedure, the JTAG programming steps are tried for 16 times at maximum, then the busy signal is put back to 0.

October 12: firmware released on the 12nd of October 2009

This firmware release (introducing modifications only on the central VP20_VME FPGA) tries to fix the problem of growing data size during data taking. A new bit, named physics_run, has been added: when 0 the firmware behaves exactly as previous releases, when 1 CARLOSrx forces JTAG reprogramming when data size exceeds 64 KBytes (at 40 MHz) or 32 KBytes (at 20 MHz). Beside that, when running the ttc_init procedure, the JTAG programming steps are tried as many times as 64, then the busy signal is put back to 0.

Year 2011

February 2011: firmware released on February 2011

This firmware release (introducing modifications only on the central FPGA) tries to handle the backpressure activation when taking data without compression (calibration runs) and increase the speed of such runs.

Year 2012

February 2012: firmware released on February 2012

This firmware release (introducing modifications only on the central FPGA) tries to handle the newly introduced SW trigger SYNC by sending a properly formatted CDH to the readout.

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